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<pre>

<a name="2"></a><span class=M>`define</span> <a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a> 16

<span class=C>/* Two half adders to create a full one */</span>
<a name="addsub1"></a><span class=K>module</span> <span class=MM>addsub1</span><a  href="index-m.html#addsub1"><img align=top border=0 alt="Index" src="v2html-i.gif"></a>(
  <a  onClick="return qs(event,this,1)"  class=SI href="#10">op</a>, <a  onClick="return qs(event,this,2)"  class=SI href="#10">oc</a>, <a  onClick="return qs(event,this,3)"  class=SO href="#11">y</a>, <a  onClick="return qs(event,this,4)"  class=SI href="#12">a</a>, <a  onClick="return qs(event,this,5)"  class=SI href="#12">b</a>, <a  onClick="return qs(event,this,6)"  class=SI href="#13">c_in</a>,
  <a  onClick="return qs(event,this,7)"  class=SO href="#14">c_out</a>, <a  onClick="return qs(event,this,8)"  class=SO href="#15">h_out</a>
);

<a name="10"></a><span class=K>input</span> <a  onClick="return qs(event,this,1)"  class=SI href="#10">op</a>, <a  onClick="return qs(event,this,2)"  class=SI href="#10">oc</a>; <span class=C>// 0: add, 1: sub
</span><a name="11"></a><span class=K>output</span> [<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>-1:0] <a  onClick="return qs(event,this,3)"  class=SO href="#36">y</a>;
<a name="12"></a><span class=K>input</span> [<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>-1:0] <a  onClick="return qs(event,this,4)"  class=SI href="#12">a</a>, <a  onClick="return qs(event,this,5)"  class=SI href="#12">b</a>;
<a name="13"></a><span class=K>input</span> <a  onClick="return qs(event,this,6)"  class=SI href="#13">c_in</a>;
<a name="14"></a><span class=K>output</span> <a  onClick="return qs(event,this,7)"  class=SO href="#34">c_out</a>;
<a name="15"></a><span class=K>output</span> <a  onClick="return qs(event,this,8)"  class=SO href="#33">h_out</a>;

<a name="17"></a><span class=K>wire</span> [<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>/2-1:0] <a  onClick="return qs(event,this,9)"  class=SW href="#31">yh</a>, <a  onClick="return qs(event,this,10)"  class=SW href="#30">yl</a>;

<span class=K>wire</span> [<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>/2-1:0]
<a name="20"></a>  <a  onClick="return qs(event,this,11)"  class=SW href="#20">ah</a> = <a  onClick="return qs(event,this,4)"  class=SI href="#12">a</a>[<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>-1:<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>/2], <a  onClick="return qs(event,this,12)"  class=SW href="#20">al</a> = <a  onClick="return qs(event,this,4)"  class=SI href="#12">a</a>[<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>/2-1:0];
<a name="21"></a><span class=K>wire</span> [<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>/2-1:0] <a  onClick="return qs(event,this,13)"  class=SW href="#27">bh</a>, <a  onClick="return qs(event,this,14)"  class=SW href="#28">bl</a>;
<a name="22"></a><span class=K>wire</span> <a  onClick="return qs(event,this,15)"  class=SW href="#22">c</a> =
  (!<a  onClick="return qs(event,this,2)"  class=SI href="#10">oc</a>) ? 0 :
  (<a  onClick="return qs(event,this,1)"  class=SI href="#10">op</a>) ? ~<a  onClick="return qs(event,this,6)"  class=SI href="#13">c_in</a> : <a  onClick="return qs(event,this,6)"  class=SI href="#13">c_in</a>;
<a name="25"></a><span class=K>wire</span> <a  onClick="return qs(event,this,16)"  class=SW href="#30">d</a>, <a  onClick="return qs(event,this,17)"  class=SW href="#31">e</a>;

<a name="27"></a><span class=K>assign</span> <a  onClick="return qs(event,this,13)"  class=SW href="#21">bh</a> = (<a  onClick="return qs(event,this,1)"  class=SI href="#10">op</a>) ? ~<a  onClick="return qs(event,this,5)"  class=SI href="#12">b</a>[<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>-1:<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>/2] : <a  onClick="return qs(event,this,5)"  class=SI href="#12">b</a>[<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>-1:<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>/2];
<a name="28"></a><span class=K>assign</span> <a  onClick="return qs(event,this,14)"  class=SW href="#21">bl</a> = (<a  onClick="return qs(event,this,1)"  class=SI href="#10">op</a>) ? ~<a  onClick="return qs(event,this,5)"  class=SI href="#12">b</a>[<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>/2-1:0] : <a  onClick="return qs(event,this,5)"  class=SI href="#12">b</a>[<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>/2-1:0];

<a name="30"></a><span class=K>assign</span> {<a  onClick="return qs(event,this,16)"  class=SW href="#25">d</a>, <a  onClick="return qs(event,this,10)"  class=SW href="#17">yl</a>} = <a  onClick="return qs(event,this,12)"  class=SW href="#20">al</a> + <a  onClick="return qs(event,this,14)"  class=SW href="#28">bl</a> + <a  onClick="return qs(event,this,15)"  class=SW href="#22">c</a>;
<a name="31"></a><span class=K>assign</span> {<a  onClick="return qs(event,this,17)"  class=SW href="#25">e</a>, <a  onClick="return qs(event,this,9)"  class=SW href="#17">yh</a>} = <a  onClick="return qs(event,this,11)"  class=SW href="#20">ah</a> + <a  onClick="return qs(event,this,13)"  class=SW href="#27">bh</a> + <a  onClick="return qs(event,this,16)"  class=SW href="#30">d</a>;

<a name="33"></a><span class=K>assign</span> <a  onClick="return qs(event,this,8)"  class=SO href="#15">h_out</a> = (<a  onClick="return qs(event,this,1)"  class=SI href="#10">op</a>) ? ~<a  onClick="return qs(event,this,16)"  class=SW href="#30">d</a> : <a  onClick="return qs(event,this,16)"  class=SW href="#30">d</a>;
<a name="34"></a><span class=K>assign</span> <a  onClick="return qs(event,this,7)"  class=SO href="#14">c_out</a> = (<a  onClick="return qs(event,this,1)"  class=SI href="#10">op</a>) ? ~<a  onClick="return qs(event,this,17)"  class=SW href="#31">e</a> : <a  onClick="return qs(event,this,17)"  class=SW href="#31">e</a>;

<a name="36"></a><span class=K>assign</span> <a  onClick="return qs(event,this,3)"  class=SO href="#11">y</a> = {<a  onClick="return qs(event,this,9)"  class=SW href="#31">yh</a>, <a  onClick="return qs(event,this,10)"  class=SW href="#30">yl</a>};

<span class=K>endmodule</span>

<span class=C>/*
=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit &lt;addsub1&gt;.
    Related source file is &quot;C:/src/pacoblaze/pacoblaze/addsub.v&quot;.
    Found 8-bit adder carry in/out for signal &lt;$n0001&gt;.
    Found 8-bit adder carry in/out for signal &lt;$n0002&gt;.
    Found 1-bit 4-to-1 multiplexer for signal &lt;c&gt;.
    Summary:
  inferred   2 Adder/Subtractor(s).
  inferred   1 Multiplexer(s).
Unit &lt;addsub1&gt; synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 2
 8-bit adder carry in/out                              : 2
# Multiplexers                                         : 1
 1-bit 4-to-1 multiplexer                              : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 2
 8-bit adder carry in/out                              : 2
# Multiplexers                                         : 1
 1-bit 4-to-1 multiplexer                              : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx.

Optimizing unit &lt;addsub1&gt; ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block addsub1, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : addsub1.ngr
Top Level Output File Name         : addsub1
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 53

Cell Usage :
# BELS                             : 67
#      LUT2                        : 34
#      LUT3                        : 1
#      MUXCY                       : 16
#      XORCY                       : 16
# IO Buffers                       : 53
#      IBUF                        : 35
#      OBUF                        : 18
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200pq208-5

 Number of Slices:                      19  out of   1920     0%
 Number of 4 input LUTs:                35  out of   3840     0%
 Number of bonded IOBs:                 53  out of    141    37%


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 12.573ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 824 / 18
-------------------------------------------------------------------------
Delay:               12.573ns (Levels of Logic = 21)
  Source:            op (PAD)
  Destination:       c_out (PAD)

  Data Path: op to c_out
                                Gate     Net
    Cell:in-&gt;out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I-&gt;O            19   0.715   1.403  op_IBUF (op_IBUF)
     LUT2:I1-&gt;O            1   0.479   0.976  bl&lt;0&gt;1 (bl&lt;0&gt;)
     LUT2:I0-&gt;O            1   0.479   0.000  addsub1_yl&lt;0&gt;lut (N4)
     MUXCY:S-&gt;O            1   0.435   0.000  addsub1_yl&lt;0&gt;cy (addsub1_yl&lt;0&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub1_yl&lt;1&gt;cy (addsub1_yl&lt;1&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub1_yl&lt;2&gt;cy (addsub1_yl&lt;2&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub1_yl&lt;3&gt;cy (addsub1_yl&lt;3&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub1_yl&lt;4&gt;cy (addsub1_yl&lt;4&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub1_yl&lt;5&gt;cy (addsub1_yl&lt;5&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub1_yl&lt;6&gt;cy (addsub1_yl&lt;6&gt;_cyo)
     MUXCY:CI-&gt;O           2   0.056   0.000  addsub1_yl&lt;7&gt;cy (d)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub1_yh&lt;0&gt;cy (addsub1_yh&lt;0&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub1_yh&lt;1&gt;cy (addsub1_yh&lt;1&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub1_yh&lt;2&gt;cy (addsub1_yh&lt;2&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub1_yh&lt;3&gt;cy (addsub1_yh&lt;3&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub1_yh&lt;4&gt;cy (addsub1_yh&lt;4&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub1_yh&lt;5&gt;cy (addsub1_yh&lt;5&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub1_yh&lt;6&gt;cy (addsub1_yh&lt;6&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.265   0.976  addsub1_yh&lt;7&gt;cy (e)
     LUT2:I0-&gt;O            1   0.479   0.681  c_out1 (c_out_OBUF)
     OBUF:I-&gt;O                 4.909          c_out_OBUF (c_out)
    ----------------------------------------
    Total                     12.573ns (8.538ns logic, 4.035ns route)
                                       (67.9% logic, 32.1% route)
*/</span>


<span class=C>/* Two separate adders */</span>
<a name="addsub2"></a><span class=K>module</span> <span class=MM>addsub2</span><a  href="index-m.html#addsub2"><img align=top border=0 alt="Index" src="v2html-i.gif"></a>(
  <a  onClick="return qs(event,this,18)"  class=SI href="#197">op</a>, <a  onClick="return qs(event,this,19)"  class=SI href="#197">oc</a>, <a  onClick="return qs(event,this,20)"  class=SO href="#198">y</a>, <a  onClick="return qs(event,this,21)"  class=SO href="#204">yl</a>, <a  onClick="return qs(event,this,22)"  class=SI href="#199">a</a>, <a  onClick="return qs(event,this,23)"  class=SI href="#199">b</a>, <a  onClick="return qs(event,this,24)"  class=SI href="#200">c_in</a>,
  <a  onClick="return qs(event,this,25)"  class=SO href="#201">c_out</a>, <a  onClick="return qs(event,this,26)"  class=SO href="#202">h_out</a>
);

<a name="197"></a><span class=K>input</span> <a  onClick="return qs(event,this,18)"  class=SI href="#197">op</a>, <a  onClick="return qs(event,this,19)"  class=SI href="#197">oc</a>; <span class=C>// 0: add, 1: sub
</span><a name="198"></a><span class=K>output</span> [<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>-1:0] <a  onClick="return qs(event,this,20)"  class=SO href="#219">y</a>;
<a name="199"></a><span class=K>input</span> [<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>-1:0] <a  onClick="return qs(event,this,22)"  class=SI href="#199">a</a>, <a  onClick="return qs(event,this,23)"  class=SI href="#199">b</a>;
<a name="200"></a><span class=K>input</span> <a  onClick="return qs(event,this,24)"  class=SI href="#200">c_in</a>;
<a name="201"></a><span class=K>output</span> <a  onClick="return qs(event,this,25)"  class=SO href="#222">c_out</a>;
<a name="202"></a><span class=K>output</span> <a  onClick="return qs(event,this,26)"  class=SO href="#221">h_out</a>;

<a name="204"></a><span class=K>output</span> [<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>/2-1:0] <a  onClick="return qs(event,this,21)"  class=SO href="#218">yl</a>;

<span class=K>wire</span> [<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>/2-1:0]
<a name="207"></a>  <a  onClick="return qs(event,this,27)"  class=SW href="#207">al</a> = <a  onClick="return qs(event,this,22)"  class=SI href="#199">a</a>[<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>/2-1:0];
<a name="208"></a><span class=K>wire</span> [<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>-1:0] <a  onClick="return qs(event,this,28)"  class=SW href="#216">bs</a>;
<a name="209"></a><span class=K>wire</span> [<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>/2-1:0] <a  onClick="return qs(event,this,29)"  class=SW href="#215">bl</a>;
<a name="210"></a><span class=K>wire</span> <a  onClick="return qs(event,this,30)"  class=SW href="#210">c</a> =
  (!<a  onClick="return qs(event,this,19)"  class=SI href="#197">oc</a>) ? 0 :
  (<a  onClick="return qs(event,this,18)"  class=SI href="#197">op</a>) ? ~<a  onClick="return qs(event,this,24)"  class=SI href="#200">c_in</a> : <a  onClick="return qs(event,this,24)"  class=SI href="#200">c_in</a>;
<a name="213"></a><span class=K>wire</span> <a  onClick="return qs(event,this,31)"  class=SW href="#218">d</a>, <a  onClick="return qs(event,this,32)"  class=SW href="#219">e</a>;

<a name="215"></a><span class=K>assign</span> <a  onClick="return qs(event,this,29)"  class=SW href="#209">bl</a> = (<a  onClick="return qs(event,this,18)"  class=SI href="#197">op</a>) ? ~<a  onClick="return qs(event,this,23)"  class=SI href="#199">b</a>[<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>/2-1:0] : <a  onClick="return qs(event,this,23)"  class=SI href="#199">b</a>[<span class=D>`</span><a  onClick="return qs(event,this,0)"  class=D href="#2">WIDTH</a>/2-1:0];
<a name="216"></a><span class=K>assign</span> <a  onClick="return qs(event,this,28)"  class=SW href="#208">bs</a> = (<a  onClick="return qs(event,this,18)"  class=SI href="#197">op</a>) ? ~<a  onClick="return qs(event,this,23)"  class=SI href="#199">b</a> : <a  onClick="return qs(event,this,23)"  class=SI href="#199">b</a>;

<a name="218"></a><span class=K>assign</span> {<a  onClick="return qs(event,this,31)"  class=SW href="#213">d</a>, <a  onClick="return qs(event,this,21)"  class=SO href="#204">yl</a>} = <a  onClick="return qs(event,this,27)"  class=SW href="#207">al</a> + <a  onClick="return qs(event,this,29)"  class=SW href="#215">bl</a> + <a  onClick="return qs(event,this,30)"  class=SW href="#210">c</a>;
<a name="219"></a><span class=K>assign</span> {<a  onClick="return qs(event,this,32)"  class=SW href="#213">e</a>, <a  onClick="return qs(event,this,20)"  class=SO href="#198">y</a>} = <a  onClick="return qs(event,this,22)"  class=SI href="#199">a</a> + <a  onClick="return qs(event,this,28)"  class=SW href="#216">bs</a> + <a  onClick="return qs(event,this,30)"  class=SW href="#210">c</a>;

<a name="221"></a><span class=K>assign</span> <a  onClick="return qs(event,this,26)"  class=SO href="#202">h_out</a> = (<a  onClick="return qs(event,this,18)"  class=SI href="#197">op</a>) ? ~<a  onClick="return qs(event,this,31)"  class=SW href="#218">d</a> : <a  onClick="return qs(event,this,31)"  class=SW href="#218">d</a>;
<a name="222"></a><span class=K>assign</span> <a  onClick="return qs(event,this,25)"  class=SO href="#201">c_out</a> = (<a  onClick="return qs(event,this,18)"  class=SI href="#197">op</a>) ? ~<a  onClick="return qs(event,this,32)"  class=SW href="#219">e</a> : <a  onClick="return qs(event,this,32)"  class=SW href="#219">e</a>;

<span class=K>endmodule</span>


<span class=C>/*
=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit &lt;addsub2&gt;.
    Related source file is &quot;C:/src/pacoblaze/pacoblaze/addsub.v&quot;.
    Found 16-bit adder carry in/out for signal &lt;$n0001&gt;.
    Found 8-bit adder carry in/out for signal &lt;$n0002&gt;.
    Found 1-bit 4-to-1 multiplexer for signal &lt;c&gt;.
    Summary:
  inferred   2 Adder/Subtractor(s).
  inferred   1 Multiplexer(s).
Unit &lt;addsub2&gt; synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 2
 16-bit adder carry in/out                             : 1
 8-bit adder carry in/out                              : 1
# Multiplexers                                         : 1
 1-bit 4-to-1 multiplexer                              : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 2
 16-bit adder carry in/out                             : 1
 8-bit adder carry in/out                              : 1
# Multiplexers                                         : 1
 1-bit 4-to-1 multiplexer                              : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx.

Optimizing unit &lt;addsub2&gt; ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block addsub2, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : addsub2.ngr
Top Level Output File Name         : addsub2
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 61

Cell Usage :
# BELS                             : 91
#      LUT2                        : 34
#      LUT3                        : 9
#      MUXCY                       : 24
#      XORCY                       : 24
# IO Buffers                       : 61
#      IBUF                        : 35
#      OBUF                        : 26
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200pq208-5

 Number of Slices:                      23  out of   1920     1%
 Number of 4 input LUTs:                43  out of   3840     1%
 Number of bonded IOBs:                 61  out of    141    43%


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 12.955ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 1012 / 26
-------------------------------------------------------------------------
Delay:               12.955ns (Levels of Logic = 21)
  Source:            op (PAD)
  Destination:       c_out (PAD)

  Data Path: op to c_out
                                Gate     Net
    Cell:in-&gt;out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I-&gt;O            27   0.715   1.721  op_IBUF (op_IBUF)
     LUT2:I1-&gt;O            2   0.479   1.040  bs&lt;0&gt;1 (bs&lt;0&gt;)
     LUT2:I0-&gt;O            1   0.479   0.000  addsub2_y&lt;0&gt;lut (N4)
     MUXCY:S-&gt;O            1   0.435   0.000  addsub2_y&lt;0&gt;cy (addsub2_y&lt;0&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub2_y&lt;1&gt;cy (addsub2_y&lt;1&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub2_y&lt;2&gt;cy (addsub2_y&lt;2&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub2_y&lt;3&gt;cy (addsub2_y&lt;3&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub2_y&lt;4&gt;cy (addsub2_y&lt;4&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub2_y&lt;5&gt;cy (addsub2_y&lt;5&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub2_y&lt;6&gt;cy (addsub2_y&lt;6&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub2_y&lt;7&gt;cy (addsub2_y&lt;7&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub2_y&lt;8&gt;cy (addsub2_y&lt;8&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub2_y&lt;9&gt;cy (addsub2_y&lt;9&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub2_y&lt;10&gt;cy (addsub2_y&lt;10&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub2_y&lt;11&gt;cy (addsub2_y&lt;11&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub2_y&lt;12&gt;cy (addsub2_y&lt;12&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub2_y&lt;13&gt;cy (addsub2_y&lt;13&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.056   0.000  addsub2_y&lt;14&gt;cy (addsub2_y&lt;14&gt;_cyo)
     MUXCY:CI-&gt;O           1   0.265   0.976  addsub2_y&lt;15&gt;cy (e)
     LUT2:I0-&gt;O            1   0.479   0.681  c_out1 (c_out_OBUF)
     OBUF:I-&gt;O                 4.909          c_out_OBUF (c_out)
    ----------------------------------------
    Total                     12.955ns (8.538ns logic, 4.418ns route)
                                       (65.9% logic, 34.1% route)
*/</span>
</pre>
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  <td><i>Created:</i></td><td><i>Tue May 29 02:37:53 2007</i></td></tr>
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